Many electronic circuits use digital-to-analog converters (DACs) for converting digital signals to corresponding analog signals. For example, cellular base stations, wireless communication systems, direct digital frequency synthesizers, signal reconstruction circuits, test equipment, high resolution imaging systems, and arbitrary waveform generators often require high resolution, high speed DACs.
A DAC (or ADC) is an important component for processing video signals and displaying still and sub pictures in imaging systems such as televisions, video tape recorders, digital cameras, and various multi-media apparatuses. More particularly, digitized video signals are common in interpolating, compressing, expanding, and displaying images in multi-media technology such as with computer systems, as well as in the televisions and digital cameras, and such digitized video signals often need to be converted to analog form after digital processing. Accordingly, enhancing the resolution of digital-to-analog converters in the video and multi-media imaging systems is desirable.
FIG. 1 shows the construction of a DAC system having buffer circuits 10 and 40, a decoder 20, a delay circuit 30, a bias voltage supply circuit 50, and a DAC core circuit 60. The buffer circuit 10, which includes two buffers 11 and 12, receives digital signals (bits) D1 through D10. The decoder 20 receives the four most significant bits D7 through D10 and generates a 15-bit digital signal having between zero and fifteen bits in a logic low state, depending on the value represented by the 4-bit input signal to decoder 30. The delay circuit 30 delays the 6-bit digital signal from the buffer 12 of the buffer circuit 10 and applies a delayed 6-bit digital signal to buffer 42 of the buffer circuit 40 when decoder 20 applies the 15-bit signal to buffer 41 of buffer circuit 40. DAC core circuit 60 receives the 15-bit and 6-bit digital signals from the buffer circuit 40 at the same time. The bias voltage supply circuit 50 generates bias voltages VBa and VBb to control the DAC core circuit 60 for generation of an appropriate output voltage Vdac for a display apparatus such as electron gun 70.
The DAC core circuit 60, as shown in FIG. 2, has twenty-one current drive circuits CURI through CUR21, each assigned to a corresponding one of the twenty-one digital signals (15 bits+6 bits). The bias voltages VBa and VBb and the digital signals D1 ' through D21' (and their complements D1B' through D21 B') control currents I1 through I21 that the current drive circuits conduct to an output summing node N1 at which output voltage Vdac is generated. When activated each of current drive circuits CUR2 to CUR6 provides about twice the current of the preceding one of circuits CUR1 to CUR5. Current drive circuits CUR7 to CUR21 all provide about the same current when respective digital signals D1' to D21' are in the logic low state. Output voltage Vdac results from a total current Isum flowing from the node N1 to a substrate voltage VSS through a resistor R.
FIG. 3 illustrates a situation where the output voltage Vdac from the DAC core circuit 60 is intended to match the shape of an analog wave. Unfortunately, when the output voltage Vdac is near a maximum voltage Vmax, drain-to-source voltages of PMOS transistors PM1 and PM2 in current drive circuits CUR1 and CUR2 are less than when output voltage is near a minimum voltage Vmin. Accordingly, currents I1 and I2 that respectively flow through current drive circuits CUR1 and CUR2 to the node N1 decrease as shown with curve C of FIG. 4 because variation in the output voltage Vdac at the node N1 affects the drain-to-source voltages of PMOS transistors PM1 and PM2. For example, current I2 from current drive circuit CUR1 is ideally one quarter (1/4) of a current I that flows into the common source node of transistors PM1 and PM1', and current I4 from current drive circuit CUR2 is ideally one half (1/2) of the current I that flows in the common source node of transistors PM2 and PM2'. Correspondingly, as shown in the curve D, currents I1' (ideally 3/4 of current I) and I2' (ideally 1/2 of current I), which flow to reference voltage VSS through respective PMOS transistors PM1' and PM2', increase as output voltage Vdac increases. The drain-to-source current Ids (of PMOS transistors PM1 and PM2) declines, as shown with curve E of FIG. 5 (curve F is an ideal form), in the saturation region so that the drain-to-source current is influenced by a .lambda.-effect (i.e., channel length modulation effect) induced from node N1. Such a decline of the current, as shown in FIG. 3, lowers levels of output voltage Vdac to levels B, which are lower than the desired levels A when output voltage Vdac is near maximum voltage Vmax. This can degrade the resolution of a display apparatus using the analog output voltage from the DAC.